Wi-Fi 6E Chipset Design
In the rapidly evolving landscape of wireless communication, Wi-Fi 6E stands out as a game-changer, promising unprecedented speeds, reduced latency, and enhanced capacity. This blog by Lumenci delves deep into the cutting-edge technology of Wi-Fi 6E chipset design, unraveling its complexity and shedding light on the meticulous design process that paves the way for a seamless and interconnected future.
Introduction
Wi-Fi 6E is the latest advancement in wireless technology, specifically an extension of the Wi-Fi 6 (802.11ax) standard. It basically operates in the 6 GHz frequency band, offering a wider spectrum with significant improvements in performance over previous Wi-Fi generations. Wi-Fi 6E brings numerous advancements, including faster speeds, low latency, reduced interference, and increased capacity, making it advantageous for high-bandwidth application requirements in multiple connected devices. Due to more available channels, it offers seamless connectivity with improved network efficiency even in highly dense environments.
Topologies
The topology behind the design of the WiFi 6E chipset basically refers to the overall architectural arrangement and the organization of multiple components within the chipset. It involves the arrangement of various functional blocks or modules such as RF Front-end components, baseband processing, interface module, memory module, and control modules. Some of the common topologies used by the circuit designers for WiFi 6E chipset are:
System-on-Chip (SoC):
This type of chipset is designed in a way that all modules, such as RF front-end, baseband processing, interface, memory, and control modules, are integrated into a single chip.
System-in-Package (SiP):
Wi-Fi 6E chipset can also be implemented as a system-in-package, where multiple modules can be implemented as separate chips, each packaged individually and finally interconnected using advanced packaging technologies.
Multi-Chip-Module:
This type of chipset can be designed as a Multi-chip module, where several modules are implemented as separate chips and integrated onto a single substrate or PCB (Printed Circuit Board).
Hybrid Integration:
This type of integration is a combination of multiple topologies such as SoC, SiP, and Multi-chip module. In this topology, some components or modules are integrated as an SoC, while the remaining are implemented as separate chips within a package (SiP) or mounted on a single substrate or PCB, such as a multi-chip module.
However, these choices of topology depend on multiple factors, including power efficiency, performance goals, design requirements, form factor constraints, etc., and also vary among different manufacturers.
Functional Blocks for Designing Wi-Fi 6E Chipset
Wi-Fi 6E chipset design consists of several circuit blocks that combinedly provide wireless connectivity. The arrangements and specifications of these circuit blocks can vary among different manufacturer chipsets. However, some functional block circuits which are common for designing Wi-Fi 6E chipsets are mentioned below:
Radio-Frequency (RF) Front-End:
RF front-end components play an essential role in ensuring efficient and reliable wireless communication. These components transmit and receive wireless signals in the designated frequency bands, enabling wireless communication between devices. Some common components are as:
Antenna
The antenna acts as an interface between the electronic signals within the chipset and the wireless medium. It basically converts electrical signals into electromagnetic waves for transmission and receives incoming electromagnetic waves for conversion into electrical signals. Different types of antennas can be integrated into these designs, such as-
Dipole Antennas
PIFA (Planar Inverted F- Antennas)
CB Antennas
MIMO (Multiple- Input Multiple-Output) Antennas
External Antennas
Some Wifi 6E chipsets also have external antennas which can be detached and replaced with other antennas. It provides flexibility toward antenna configuration to optimize signal transmission and reception. This type of design commonly employs devices like routers and access points.
Low-Noise Amplifiers
The Low-Noise Amplifier is particularly responsible for amplifying the weak incoming RF signals received from the antenna. It boosts the signal strength while maintaining the noise figure and linearity, thereby improving the receiver sensitivity, dynamic range, and enhancing the overall signal quality.
Filters
Filters play a crucial role in RF front-end design by allowing only the desired frequency range and attenuating the unwanted signals and noise from the desired Wifi 6E frequency bands. Band-pass filters and low-noise filters are some of the filters used in the Wifi 6E chipset design. Designers can utilize several techniques like LC (Inductor-Capacitor), SAW (Surface Acoustic Wave), or BAW (Bulk Acoustic Wave) filters to meet specific requirements and standards.
Mixers
Mixers play an important role in the process of frequency conversion. In Wifi 6E, the mixers are utilized for both the Upconversion and Downconversion of signals, which enables the transmission and reception of data within the designated 6 GHz frequency range. During Upconversion, the mixers take the baseband signal and combine it with the high-frequency local oscillator (LO) to generate the desired carrier frequency for transmission. Conversely, during Downconversion, the mixer combines the received signal with a local oscillator (LO) signal to convert it to a baseband signal for further processing.
Mixer components are designed to handle the increased signal bandwidth, ensuring accurate signal conversion while preserving the integrity of transmitted and received data. Mixers also have the ability to reject image frequencies to minimize interference and maintain signal quality. Several factors such as linearity, dynamic range, low noise figure, spectral purity, and isolation between input and output ports to minimize leakage were also kept in mind while designing the mixer components for Wifi 6E chipsets. This helps in ensuring low power consumption with good overall efficiency among chipsets.
Different types of Mixers are designed to perform frequency conversion for efficient wireless communication. Some are the mixer architectures are as follows:
Passive Mixers
Active Mixers
Single-balanced Mixers
Double-balanced Mixers
Gilbert Cell Mixer
Image-Reject Mixer
However, different manufacturers employed different types of mixers to balance performance, power consumption, available area, and cost to ensure optimal frequency conversion for efficient and reliable wireless communication with the WiFi 6E chipsets.
IF (Intermediate Frequency) Amplifiers
IF Amplifiers are typically employed in the WiFi 6E chipset design to amplify, and process signals at the intermediate frequency stage of the receiver. Once the RF signals are downconverted to a lower intermediate frequency, the IF amplifier boosts the weak signal to a suitable level for further demodulation and decoding. Designers can optimize the IF amplifier for low noise figure, high linearity, gain, dynamic range, and available size to meet specific requirements.
Analog-to-Digital Converter (ADC)
The Analog-to-Digital Converter is a component used in the receiver side of the Wifi 6E chipset design to convert analog signals into digital signals for further analysis in the baseband domain. When the signals are received from the antenna, the RF analog signals are amplified and filtered. These signals are then processed in ADC to convert them from RF analog signals to digital signals that can be demodulated and decoded by the Digital signal processing (DSP) unit. Several factors, such as desired resolution, sampling rate, low signal-to-noise ratio (SNR), and dynamic range, are kept in consideration for designing the ADC architectures.
Digital-to-Analog Converter (DAC)
The Digital-to-Analog Converter is a component basically used in the transmitter side of the Wifi 6E chipset design to convert digital signals, such as modulated and encoded data, into analog signals required for wireless transmission. After getting the digital signals from the baseband processing side, the DAC can convert these digital signals into analog signals that can be further amplified and transmitted over air via an antenna. Designers can select DAC architectures with appropriate resolution, dynamic range, and sampling rate to accurately reconstruct the analog signals for further transmitting.
Baseband Processor
The Baseband processor used in the Wifi 6E chipset is primarily used for handling various tasks such as modulation and demodulation, error correction, packet handling, MAC layer processing, channel estimation and equalization, timing synchronization, protocol handling, and control, etc.
It can also have a digital signal processing (DSP) unit, application-specific integrated circuits (ASICs), microprocessors, etc., to ensure reliable and efficient data transmission.
Power Amplifiers
The power amplifier plays an important role in the Wifi 6E chipset design to amplify the radio frequency signals before transmission. It is responsible for taking the low-power RF signals generated by the baseband processor and amplifying them to a level suitable for wireless transmission. It ensures that signals transmitted to the antenna are strong enough to efficiently propagate and reach the desired destination. Different types of power amplifiers can be employed in chipsets depending on several factors like frequency range, power efficiency requirement, linearity and distortion characteristics, and overall system design. Some of the common types of power amplifiers are:
·Class A Power Amplifiers
Class AB Power Amplifiers
Class D Power Amplifiers
Envelope Tracking (ET) Power Amplifiers
Dynamic Power Amplifiers
Duplexers
Duplexers are designed to enable simultaneous transmission and reception of signals on the same frequency band. It allows for efficient sharing of the frequency spectrum, enabling seamless bidirectional communication without interference. It operates on the principle of frequency division, allowing the WiFi 6E chipset to share the same antenna for both transmission and reception while using different frequency bands. Certain factors such as low insertion loss, high isolation between transmit and receive signal path, bandwidth requirements, and size constraints are kept in mind while designing duplexers to get optimal performance.
RF Switch
The RF switch or Antenna switch used in the Wifi 6E design enables switching between multiple antennas used for transmission and reception. It enables antenna diversity, where multiple antennas are used to enhance signal quality, mitigating multipath effects, and providing desired coverage and performance.
Fractional-N-PLL Frequency Synthesizers
The Fractional-N-PLL frequency synthesizer allows for precise and flexible frequency tuning, enabling this chipset to adapt to different sub-bands within the 6 GHz frequency range and dynamically select the optimal operating frequency. This flexibility ensures efficient utilization of the available spectrum, minimizing interference and maximizing performance. Additionally, the Fractional-N-PLL provides fine frequency resolution, enabling fine control over the carrier frequency. This fine resolution is very important in Wi-Fi 6E, where channel spacing is narrower as compared with previous Wi-Fi standards.
WiFi 6E also supports channel bonding, which involves combining the frequency of adjacent channels, resulting in increased bandwidth and faster connections. Fractional-N-PLL also facilitates frequency hopping, rapidly switching between frequencies to mitigate interference and enhance signal quality. This also ensures spectral purity, generates a clean carrier signal, and offers power efficiency with optimized energy consumption. Overall, PLL ensures the generation of a stable and precise clock signal essential for frequency synthesis and modulation/demodulation process.
Voltage -Controlled Oscillators (VCO)
The VCO is a part of the PLL loop and a key component that generates the carrier frequency used for wireless transmission in Wi-Fi 6E. It generates a variable frequency output that can be adjusted to different channels within the 6 GHz frequency band, enabling flexibility in selecting the operating frequency. The VCO’s ability to generate and tune specific frequencies accurately is vital in achieving the precise frequency synthesis, modulation, and demodulation process.
Matching Networks
Matching networks are implemented in the Wifi 6E chipset design to optimize impedance matching between the RF components and the antenna. A matching network typically includes several components like Baluns, matching transformers, L-C components, transmission line sections, and multiple variable components. These components are specifically incorporated in the design to ensure optimal power transfer, minimize signal reflections, and enhance the overall RF performance of the Wifi 6E chipset.
Control Circuits and Interface Circuit Blocks
Several circuit blocks, such as control circuits, manage the calibration and dynamic adjustments, and biasing circuits provide the required current and voltage to ensure the proper functioning of other circuit blocks, optimizing their overall performance and adapting to changing network conditions.
Interface circuit blocks are also employed in the Wifi 6E chipset design, such as PCIe (Peripheral Component Interconnect Express), USB (Universal Serial Bus), SPI (Serial Peripheral Interface), I2C (Inter-Integrated circuits), or other custom interfaces as per design requirements.
Power Management
Power management circuit blocks are essentially designed in a Wifi 6E chipset for efficient power regulation, control, and optimization. These circuits include voltage regulators, power switches, power sequencing circuits, and sub-circuits for power control and monitoring functions such as sleep mode, idle mode, etc. These circuit blocks ensure a stable power supply, capable of enabling low-power states and enhancing overall power efficiency.
Different manufacturers and designers have implemented the above-mentioned circuit blocks in different ways to meet their specific requirements and goals. Some of the publicly available designs and their micrographs are mentioned below:
This document represents a 3.5-to-6.2-GHz high linearity mixer-first superheterodyne receiver chipset that utilizes gigahertz intermediate-frequency (IF) acoustic filters and a Weaver-like mixed-domain recombination architecture. The chipset is fabricated using a 65-nm CMOS process technology. Fig. 1 represents the different fabricated chips that are packaged in the QFN (Quad Flat no-lead) and mounted on an FR-4 PCB (printed circuit board) with the two 2.6 GHz BAW filters (Qorvo QPQ1285). The Passive mixer front-end IC shows FE mixer switches (commutated switches), high-pass filters, local oscillators, on-chip capacitors, and transformer balun. Further, the FE chip is connected with the IF chip via bond wire and Qorvo filters. The IF receiver chip shows the low-noise amplifier (LNA), 4-phase passive mixer, and vector-modulators-based complex recombination block.
Reference 1 - Fig.1. Mixer-first acoustic-filtering chipset on a PCB with CMOS die photos.
In this document, the authors (who belong to Adveos Microelectronic Systems) present a fractional-N PLL frequency synthesizer with self-calibration digital loop engines for fast frequency acquisition and noise-driven optimization of loop filter bandwidth, VCO frequency, and amplitude control. The PLL is fabricated in a 28nm FDSOI (Fully-Depleted Silicon-On-Insulator) CMOS technology. Fig. 2 represents the PLL micrograph which shows two voltage-controlled oscillators for low and high-frequency range (VCOL and VCOH), dual-edge phase-frequency detector (PFD)/ charge pump, loop filter, multi-modulus divider, bandgap reference circuit, and calibration logic (Cal) circuit.
Reference 2 - Fig.2. PLL Micrograph
This document presents a monolithic 3-5 GHZ carrier-less IR-UWB Transceiver system. The proposed IR-UWB transceiver is implemented in a 0.13 µm 1P8M CMOS technology and the die area is 2 mm×2 mm. The chip is bonded to the 4-layer FR-4 PCB with chip-on-board (COB) assembly. Fig. 3 represents the IR-UWB Transceiver micrograph showing a low-noise amplifier (LNA) with an active balun, correlator circuit which eliminates the sample-and-hold circuits, programmable gain amplifier (PGA), comparator for digital quantization, 8-step pulse generator, synchronization circuit (Sync) implemented to have data and clock synchronized at the output of the receiver, and output buffer implemented to drive the antenna.
Reference 3 - Fig. 3. IR-UWB Transceiver Micrograph
This document presents the design of a high linear high-power silicon–germanium (SiGe) heterojunction bipolar transistor (HBT) 802.11ac/ax wireless local area network (WLAN) power amplifiers (PAs). This document also has a proposed 4-way output transformer balun, and a built-in 2nd-harmonic short is demonstrated by using a novel multi-layered metallization scheme. Different chip layout contains laterally and vertically arranged SiGe HBT array at the output stage of the Power Amplifier. The two chipsets were fabricated in Global Foundries 350nm SiGe BiCMOS technology. Fig. 4 represents the chip micrograph of three-stage (corresponds to class-A, class-AB, and deep class-AB modes) SiGe HBT Power Amplifier with lateral and vertical arrangements configurations (at the output stage) showing four-way transformer balun, thermally compensated dynamic bias circuits includes current mirror circuits and diodes, inductors and connection pads (Vcc, RFout, EN, VB, etc.).
Reference 4 - Fig.4. Chip Micrograph (a) Power Amplifier (PA) with LA (lateral arrangement) output stage, (b) Power Amplifier with VA (vertical arrangement) Configuration
This document presents a fully integrated dual-band DTC-based polar Digital Transmitter (P-DTX) supported for Wi-Fi 6E Applications. This architecture presents filter-free DDRF (Digital-direct RF) that introduces targeted noise-shaping (TaNS). TaNS attenuates quantization noise at offsets between one and ten times the bandwidth by moving it far out-of-band (OOB). The prototype is fabricated in 28-nm CMOS technology with an active die area (0.022mm2 excluding SRAM area). Fig. 5 represents the die micrograph showing Digital Signal Processing block (DSP), SRAM, sub-block containing Clock Division circuit (Clk Div), I/Q based mixing H-bridge DAC encoder, current biasing circuit (I Bias), matching network, and connection pads.
Reference 5 - Fig.5. Die Micrograph
Author
Mayank Gupta
Senior Associate at Lumenci
Mayank has 7+ years of experience related to Semiconductor devices and photomask fabrication. He has co-authored several research papers in the semiconductor domain. His work at Lumenci in multiple services like Patent Infringement Analysis, Technical Analysis, and EoU/Claim Charts in Semiconductors, Telecommunication, Networking, and Digital Payments domains. He holds a Bachelor of Engineering (B.E.) degree in Electronics and Instrumentation from MITM Indore and a Master of Technology (MTech.) degree in Microelectronics and VLSI Design from Motilal Nehru National Institute of Technology (MNNIT), Allahabad, India.