PATENT LITIGATION | SEMICONDUCTOR REVERSE ENGINEERING

Patent litigation reverse engineering

Semiconductor Reverse Engineering

Methodical approach to extract the right evidence

 
Semiconductor reverse engineering service

Semiconductor Technology Experience

Integrated Single-Chip Transceiver

RF - System on Chip (RF-SoC)

Frequency Synthesizer

Graphics Processing Units (GPU)

Integrated Programmable Gain Amplifier

Head Mounted Display (HMD)

Phase Locked Loop (PLL)

Microelectromechanical Systems (MEMS)

Flash LED

Signal Processor

Vertical Cavity Surface Emitting Laser (VCSEL)

NAND Flash Memory

 

Lumenci experts have filed declarations in the US and EU

 

Product Teardowns 

Identify the product, package, internal boards, and components

Devise Delayering and Imaging

Identity various layers, cross-section analysis, detailed imaging

Circuit Extraction & Analytical Imaging

Delayer to transistor level, then extract interconnections and components to create schematics

Materials Analysis

Examine the structure and materials to see how it is manufactured and what it is made of

Lumenci experts have filed semiconductor declarations

Product Teardown Experience

Lumenci uses a sophisticated step-by-step approach to perform a teardown of complex hardware products.

Process of product teardown
Analytical imaging for semiconductor
Semiconductor reverse engineering for a Circuit chip

Network Devices

Access Points (AP), Base Stations, Routers, Switches

User Equipment

Laptop, Mobile Phone, Tablet

Integrated Circuits

Logic Gates, Flip-Flops, Multiplexers, Wireless Transceivers, RFIC

IoT Devices

Zigbee, Bluetooth Low Energy (BLE), Z-Wave

LED

Flash and Displays

AR/VR Systems

Head Mounted Display (HMD), Haptics, Controllers

Device Delayering and Imaging

Circuit schematics analysis and device delayering

Lumenci’s delayering lab extracts circuit schematics by processing individual metal layers and polysilicon layer in an Integrated Circuit (IC) Chip by following the below two processes.

Etching and Polishing

We use both wet etch and dry (plasma) etch for different layers within the chip using proprietary techniques

Cross Sectional Imaging

We use Optical/SEM/TEM/FIB/EDS tools to image and analyze regions of interest during delayering